1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various methods of forming doped epitaxial silicon germanium (SixGe1-x) material on semiconductor devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, e.g., field effect transistors (NMOS and PMOS transistors), resistors, capacitors, etc. A field effect transistor, irrespective of whether an NMOS transistor or a PMOS transistor is considered, typically comprises doped source and drain regions that are formed in a semiconducting substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region. Such transistor devices come in a variety of shapes and forms, e.g., planar transistor devices, FinFET devices, etc.
The formation of epitaxial semiconductor material, such as SiGe, SiC, is a very common process operation when manufacturing semiconductor devices. For example, such epi semiconductor materials are formed in various locations on various areas of the integrated circuit devices. Such epi semiconductor materials are frequently formed in the source/drain regions of transistor devices. More specifically, it is often the case that transistor devices are formed with raised or embedded source/drain regions that include an epi semiconductor material. In general, a raised source/drain region involves the formation of such epi semiconductor material above the surface of the semiconducting material, whereas formation of an embedded source/drain region involves formation of a recess in the substrate and thereafter filling the recess with the epi semiconductor material.
In manufacturing PMOS devices, device manufacturers typically form epi SiGe materials in the source/drain regions of the device. Since the device is a PMOS device, the source/drain regions must eventually be doped with a P-type dopant material, e.g., boron, boron di-fluoride, etc., for the device to operate as intended. In many cases, it is desirable to form such SiGe materials with different germanium content and with different dopant concentration levels. However, using existing processing techniques, it is very difficult to form an SiGe layer with a relatively high percentage of germanium (greater than 50% Ge) and a relatively high concentration of P-type dopant (e.g., 2-3e20 ions/cm3). One prior art technique for forming such an SiGe layer involves epi growth of a single layer of SiGe0.4 (40% Ge) with in situ doping of the P-type dopant such that the resulting single layer of SiGe0.4 has a dopant concentration of about 2-3e20 ions/cm3 of the P-type dopant material. Another prior art technique for forming such an SiGe layer involves epi growth of a single layer of SiGe0.4 (40% Ge) and thereafter performing an ion implantation process to implant the P-type dopant such that the resulting single layer of SiGe0.4 has a dopant concentration of about 2-3e20 ions/cm3 of the P-type dopant material. However, performing ion implantation processes can generate a significant amount of lattice defects, thereby making the nanostructured region defective. Unfortunately, in the case of forming the P-doped epi SiGe layer with in situ doping, if the germanium percentage is increased, there will be an associated decrease in the amount of the P-type dopant that can be incorporated into the layer of epi SiGe material during the epi formation process.
The present disclosure is directed to various methods of forming doped epitaxial SiGe material on semiconductor devices that may solve or reduce one or more of the problems identified above.